Semiconductor device geometries (i.e., integrated circuit design rules) have decreased dramatically in size since integrated circuit (IC) devices were first introduced several decades ago. ICs have generally followed “Moore's Law,” which means that the number of devices fabricated on a single integrated circuit chip doubles every two years. Today's IC fabrication facilities are routinely producing 65 nm (0.065 μm) feature size devices, and future fabs will soon be producing devices having even smaller feature sizes.
As IC design rules shrink, an increasing trend in semiconductor manufacturing is utilizing single-wafer processing for a variety of fabrication steps, including plasma etching and deposition chambers. Single-wafer reactors must be designed to unobtrusively secure the wafer (or other substrate-type) during processing, while controlling both temperature and temperature uniformity across the wafer.
Mechanical wafer clamps which engage a portion of front surfaces of the wafer where processing is to be performed potentially create process uniformity problems by interfering with gas flow, altering plasma distribution, and acting as a heat sink. If improperly designed, mechanical wafer clamps may also produce particulates with resulting contamination of the wafer as well as other problems.
An electrostatic chuck (ESC) uses an electrostatic potential to hold a wafer in place during processing, thus avoiding the problems of mechanical clamping by having contact with only the back side of the wafer. Electrostatic chucks operate by inducing opposing charges on the substrate and the chuck thereby resulting in an electrostatic attraction between the chuck and the substrate. A degree of attraction is dependent on an amount of charge induced as well as a rate at which the charge dissipates due to conductive effects. Voltage biasing is employed to induce and control the electrostatic force and may be applied for only a portion of a processing cycle, for example, just after a substrate is transferred to the chuck. Alternatively, voltage biasing may be applied continuously throughout a processing cycle. For instance, using the conduction properties of plasma can provide a means of electrical connection to one terminal of a ESC and wafer system.
Various types of electrostatic chucks may include consumable (i.e., sacrificial) edge rings positioned below and around the substrate for purposes of confining plasma to the area immediately proximate to and above the substrate. The edge rings may also protect the ESC from erosion by the plasma.
With reference to FIG. 1, a portion of an exemplary prior art ESC structure 100 includes an anodized aluminum base 101, a heater bond layer 103, a heater 105, a heater plate 107, and a ceramic bond layer 109. The ESC structure 100 is capped with a ceramic top piece 111. The heater bond layer 103, heater 105, heater plate 107, and ceramic bond layer 109 are protected from direct contact with a surrounding plasma environment and caustic chemicals by an edge bonding seal 113. The edge bonding seal 113 thus protects the heater 105, the heater plate 107, and the heater 103 and ceramic 109 bonding layers from plasma erosion.
The heater bond layer 103 is typically comprised of a silicone layer impregnated with silica (e.g., amorphous SiOx). The heater 105 is frequently comprised of metallic resistance elements encapsulated in a polyimide while the heater plate 107 is typically fabricated from aluminum. A ceramic-filled (e.g., alumina (Al2O3)) silicone material is commonly employed for the ceramic bond layer 109. The ceramic top piece 111 is commonly fabricated from alumina and is configured to allow a substrate 115, such as a silicon wafer, to be securely held in place over the ceramic top piece 111.
An edge ring 117 is typically circular in overall shape and is secured to a periphery of an inner portion of the exemplary prior art ESC structure 100. The edge ring 117 is placed concentrically about the inner portion of the ESC structure 100 and features a vertical, single-surface inner diameter. The single-surface inner diameter constrains the edge ring 117 against the aluminum base 101, the edge bonding seal 113, and the ceramic top piece 111 thus nominally centering the edge ring 117.
In general, an edge ring (e.g., a hot edge ring, HER) that runs too hot during high power polymerizing chemistry in a plasma reactor forces polymers to the edges of a substrate (due to thermophoretic forces). The increased level of polymers on or near the edges of the substrate reduces critical dimensions (CDs) of planned features on the substrate. In contrast, if the edge ring is running too cool, then polymer deposited on the edge ring itself increases thereby causing increased CDs on or near the edges of the substrate (i.e., the thermal gradient between the substrate and the edge ring forces polymer precursors to deposit on the edge ring).
Therefore, a balance between hot and cool areas on the ESC must be achieved to allow proper CD uniformities across the surface of a substrate. Additionally, an optimal thermal balance configuration to achieve expected CD results must be achieved without incurring productivity issues that are unique for both differing chemistries and plasma power levels.
Therefore, what is needed is a thermal interface system to balance a temperature of an edge ring between running too hot or too cold. The thermal interface system should be quickly and easily configured for different processes (i.e., the system should be readily adjustable in the field). Additionally, the temperature of the edge ring should be readily tailored through the thermal interface system for a given set of operating parameters, such as plasma power level.